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| Temperature Sensor with Look Up Table Memory and DAC FEATURES * Single Programmable Current Generator --1.6 mA max. --8-bit (256 Step) Resolution --Internally Programmable full scale Current Outputs * Integrated 8-bit A/D Converter * Internal Voltage Reference * Temperature Compensation --Internal Sensor ---40C to +100C Range --2.2C / step resolution --EEPROM Look-up Table * Hot Pluggable * Write Protection Circuitry --Xicor BlockLockTM --Logic Controlled Protection * 2-wire Bus with 3 Slave Address Bits * 3 V to 5.5 V, Single Supply Operation * Package --14-lead TSSOP APPLICATIONS * * * * * PIN Diode Bias Control RF PA Bias Control Temperature Compensated Process Control Laser Diode Bias Control Fan Control * * * * * * * X96011 Motor Control Sensor Signal Conditioning Data Aquisition Applications Gain vs. Temperature Control High Power Audio Open Loop Temperature Compensation Close Loop Current, Voltage, Pressure, Temperature, Speed, Position Programmable Voltage sources, electronic loads, output amplifiers, or function generator DESCRIPTION The X96011 is a highly integrated bias controller which incorporates a digitally controlled Programmable Current Generator, and temperature compensation using one look-up table. All functions of the device are controlled via a 2-wire digital serial interface. The temperature compensated Programmable Current Generator varies the output current with temperature according to the contents of the associated nonvolatile look-up table. The look-up table may be programmed with arbitrary data by the user, via the 2-wire serial port, and an internal temperature sensor is used to control the output current response. BLOCK DIAGRAM Voltage Reference Mux DAC IOUT ADC Mux Look-up Table Temperature Sensor SDA SCL WP A2, A1, A0 REV 1.8 6/24/03 Control & Status 2-Wire Interface www.xicor.com 1 of 25 X96011 PIN CONFIGURATION A0 A1 A2 Vcc WP SCL SDA 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC NC NC Vss NC NC IOUT TSSOP 14L ORDERING INFORMATION Part Number X96011V14I Temperature Range I = -40 to 100C Package 14-Lead TSSOP REV 1.8 6/24/03 www.xicor.com 2 of 25 X96011 PIN ASSIGNMENTS TSSOP Pin 1 2 3 4 5 Pin Name A0 A1 A2 Vcc WP Pin Description Device Address Select Pin 0. This pin determines the LSB of the device address required to communicate using the 2-wire interface. The A0 pin has an on-chip pull-down resistor. Device Address Select Pin 1. This pin determines the intermediate bit of the device address required to communicate using the 2-wire interface. The A1 pin has an on-chip pull-down resistor. Device Address Select Pin 2. This pin determines the MSB of the device address required to communicate using the 2-wire interface. The A2 pin has an on-chip pull-down resistor. Supply Voltage. Write Protect Control Pin. This pin is a CMOS compatible input. When LOW, Write Protection is enabled preventing any "Write" operation. When HIGH, various areas of the memory can be protected using the Block Lock bits BL1 and BL0. The WP pin has an on-chip pull-down resistor, which enables the Write Protection when this pin is left floating. Serial Clock. This is a TTL compatible input pin. This input is the 2-wire interface clock controlling data input and output at the SDA pin. Serial Data. This pin is the 2-wire interface data into or out of the device. It is TTL compatible when used as an input, and it is Open Drain when used as an output. This pin requires an external pull up resistor. Current Generator Output. This pin sinks or sources current. The magnitude and direction of the current is fully programmable and adaptive. The resolution is 8 bits. No Connect. No Connect. Ground. No Connect. No Connect. No Connect. 6 7 SCL SDA 8 9 10 11 12 13 14 IOUT NC NC Vss NC NC NC REV 1.8 6/24/03 www.xicor.com 3 of 25 X96011 ABSOLUTE MAXIMUM RATINGS All voltages are referred to Vss. Temperature under bias ...................-65C to +100C Storage temperature ........................-65C to +150C Voltage on every pin except Vcc................ -1.0V to +7V Voltage on Vcc Pin............................................. 0 to 5.5V D.C. Output Current at pin SDA...................... 0 to 5 mA D.C. Output Current at pins Iout........................-3 to 3mA COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Lead temperature (soldering, 10 seconds).........300C RECOMMENDED OPERATING CONDITIONS Parameter Temperature Temperature while writing to memory Voltage on Vcc Pin Voltage on any other Pin Min. -40 0 3 -0.3 Max. +100 +70 5.5 Vcc + 0.3 Units C C V V REV 1.8 6/24/03 www.xicor.com 4 of 25 X96011 ELECTRICAL CHARACTERISTICS (Conditions are as follows, unless otherwise specified) All typical values are for 25C ambient temperature and 5 V at pin Vcc. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin Vss. Bit 7 in control register 0 is "1", while other bits in control registers are "0". 400kHz TTL input at SCL. SDA pulled to Vcc through an external 2K resistor. 2-wire interface in "standby" (see notes 1 and 2 below). WP, A0, A1, and A2 floating. Symbol Iccstby Iccfull Parameter Standby current into Vcc pin Full operation current into Vcc pin Nonvolatile Write current into Vcc pin Min Typ Max 2 6 Unit mA mA Test Conditions / Notes Iout floating, sink mode 2-wire interface reading from memory, Iout connected to Vss, DAC input bytes: FFh Average from START condition until tWP after the STOP condition WP: Vcc, Iout floating, sink mode VRef unloaded. V(WP), V(A0), V(A1), and V(A2) from 0V to Vcc Iccwrite 4 mA IPLDN On-chip pull down current at WP, A0, A1,and A2 SCL and SDA, input Low voltage SCL and SDA, input High voltage SCL and SDA input current SDA output Low voltage SDA output High current WP, A0, A1, and A2 input Low voltage WP, A0, A1, and A2 input High voltage Temperature sensor range Power on reset threshold voltage Vcc Ramp Rate ADC enable minimum voltage 0 1 20 A VILTTL VIHTTL IINTTL VOLSDA IOHSDA VILCMOS VIHCMOS TSenseRange VPOR VccRamp VADCOK 0.8 2.0 -1 0 0 0 0.8 x Vcc -40 1.5 0.2 2.6 10 0.4 100 0.2 x Vcc Vcc 100 2.8 50 2.8 V V A V A V V C V mV / s V See Figure 8. See note 3. Pin voltage between 0 and Vcc, and SDA as an input. I(SDA) = 2 mA V(SDA) = Vcc Notes: 1. The device goes into Standby: 200 ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby t WC after a STOP that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the correct Slave Address Byte. 2. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. This parameter is periodically sampled and not 100% tested. REV 1.8 6/24/03 www.xicor.com 5 of 25 X96011 D/A CONVERTER CHARACTERISTICS (See pg. 5 for standard conditions) Symbol IFS OffsetDAC FSErrorDAC DNLDAC INLDAC Parameter Iout full scale current Iout D/A converter offset error Iout D/A converter full scale error Iout D/A converter Differential Nonlinearity Iout D/A converter Integral Nonlinearity with respect to a straight line through 0 and the full scale value I1 Sink Voltage Compliance I1 Source Voltage Compliance I1 overshoot on D/A Converter data byte transition I1 undershoot on D/A Converter data byte transition I1 rise time on D/A Converter data byte transition; 10% to 90% Temperature coefficient of output current Iout Min 1.56 1 -2 -0.5 -1 Typ 1.58 Max 1.6 1 2 0.5 1 Unit mA LSB LSB LSB LSB Test Conditions / Notes DAC input Byte = FFh, Source or sink mode, V(Iout) is Vcc-1.2V in source mode and 1.2V in sink mode. See notes 1 and 2. VISink VISource IOVER IUNDER trDAC TCOI1I2 1.2 0 Vcc Vcc-1.2 0 0 V V A A s ppm/ C In this range the current at I1 vary < 1% In this range the current at I1 vary < 1% DAC input byte changing from 00h to FFh and vice versa, V(I1) is Vcc-1.2V in source mode and 1.2V in sink mode. See note 3. See Figure 5. 5 30 200 Notes: 1. LSB is defined as [2 x V(VRef)] divided by the resistance between R1 or R2 to Vss. 255 3 2. OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed in LSB. FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC. DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNLDAC. INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB. 3. These parameters are periodically sampled and not 100% tested. REV 1.8 6/24/03 www.xicor.com 6 of 25 X96011 A/D CONVERTER CHARACTERISTICS (See pg. 5 for standard conditions) Symbol ADCTIME Parameter A/D converter conversion time Min Typ Max 9 Unit ms Test Conditions / Notes Proportional to A/D converter input voltage. This value is maximum at full scale input of A/D converter. ADCfiltOff = "1" See notes 1 and 2 The ADC is monotonic OffsetADC FSErrorADC DNLADC INLADC A/D converter offset error A/D converter full scale error A/D Converter Differential Nonlinearity A/D converter Integral Nonlinearity 0.52 1 1 0.5 1 0.55 0.58 LSB LSB LSB LSB C See note 3 TempStepADC Temperature step causing one step increment of ADC output Out25ADC ADC output at 25C 011101012 Notes: 1. "LSB" is defined as V(VRef)/255, "Full Scale" is defined as V(VRef). 0.5 x V(VRef) 2. OffsetADC: For an ideal converter, the first transition of its transfer curve occurs at above zero. Offset error is the 255 amount of deviation between the measured first transition point and the ideal point. 254.5 x V(VRef) FSErrorADC: For an ideal converter, the last transition of its transfer curve occurs at . Full Scale Error is the 255 amount of deviation between the measured last transition point and the ideal point, after subtracting the Offset from the measured curve. DNLADC: DNL is defined as the difference between the ideal and the measured code transitions for successive A/D code outputs expressed in LSBs. The measured transfer curve is adjusted for Offset and Fullscale errors before calculating DNL. INLADC: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is also defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured transfer curve is adjusted for Offset and Fullscale errors before calculating INL. 3. These parameters are periodically sampled and not 100% tested. [ ] [ ] REV 1.8 6/24/03 www.xicor.com 7 of 25 X96011 2-WIRE INTERFACE A.C. CHARACTERISTICS Symbol fSCL tIN (4) Parameter SCL Clock Frequency Pulse width Suppression Time at inputs SCL Low to SDA Data Out Valid Time the bus free before start of new transmission Clock Low Time Clock High Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time SDA and SCL Rise Time SDA and SCL Fall Time WP Setup Time WP Hold Time Capacitive load for each bus line Min 1(3) Typ Max 400 50 900 Units kHz ns ns ns Test Conditions / Notes See "2-Wire Interface Test Conditions" (below), See Figure 1, Figure 2 and Figure 3. tAA(4) tBUF(4) tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR (4) 1300 1.3 0.6 600 600 100 0 600 50 20 +0.1Cb(1) 20 +0.1Cb(1) 600 600 400 300 300 1200(3) 1200 (3) s s ns ns ns s ns ns ns ns ns ns pF tF(4) tSU:WP(4) tHD:WP(4) Cb (4) 2-WIRE INTERFACE TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times, between 10% and 90% Input and Output Timing Threshold Level External Load at pin SDA 10 % to 90 % of Vcc 10 ns 1.4V 2.3 k to Vcc and 100 pF to Vss NONVOLATILE WRITE CYCLE TIMING Symbol tWC (2) Parameter Nonvolatile Write Cycle Time Min Typ 5 Max 10 Units ms Test Conditions / Notes See Figure 3 Notes: 1. Cb = total capacitance of one bus line (SDA or SCL) in pF. 2. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. The minimum frequency requirement applies between a START and a STOP condition. 4. These parameters are periodically sampled and not 100% tested. REV 1.8 6/24/03 www.xicor.com 8 of 25 X96011 TIMING DIAGRAMS Figure 1. Bus Timing tF SCL tSU:STA SDA IN tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW tR tAA SDA OUT tDH tBUF Figure 2. WP Pin Timing START SCL Clk 1 STOP SDA IN tSU:WP WP tHD:WP Figure 3. Non-Volatile Write Cycle Timing SCL SDA 8th bit of last byte ACK tWC Stop Condition Start Condition REV 1.8 6/24/03 www.xicor.com 9 of 25 X96011 XICOR SENSOR CONDITIONER PRODUCT FAMILY Features / Functions Look Up Table Organization Dual Bank Single Bank FSO Current DAC Setting Resistors Ext Device X96010 Title Sensor Conditioner with Dual Look-Up Table Memory and DACs Temperature Sensor with Look-Up Table Memory and DAC Universal Sensor Conditioner with Dual Look-Up Table Memory and DACs Internal Temperature Sensor No External Sensor Input Yes Internal Voltage Reference Yes VREF Input / Ouput Yes General Purpose EEPROM No # of DACs Dual X96011 Yes No Yes No No Single Int X96012 Yes Yes Yes Yes Yes Dual Bank Dual Ext / Int FSO = Full Scale Output, Ext = External, Int = Internal DEVICE DESCRIPTION The combination of the X96011 functionality and Xicor's QFN package lowers system cost, increases reliability, and reduces board space requirements. The on-chip Programmable Current Generator may be independently programmed to either sink or source current. The maximum current generated is determined by using an externally connected programming resistor, or by selecting one of three predefined values. Both current generators have a maximum output of 1.6 mA, and may be controlled to an absolute resolution of 0.39% (256 steps / 8 bit). The current generator is driven using either an onboard temperature sensor or Control Registers. The internal temperature sensor operates over a very broad temperature range (-40C to +100C). The sensor output drives an 8-bit A/D converter. The six MSBs of the ADC output select one of 64 bytes from the nonvolatile look-up table (LUT). The contents of the selected LUT row (8-bit wide) drives the input of an 8-bit D/A converter, which generates the output current. All control and setup parameters of the X96011, including the look-up table, are programmable via the 2-wire serial port. REV 1.8 6/24/03 www.xicor.com 10 of 25 X96011 PRINCIPLES OF OPERATION CONTROL AND STATUS REGISTERS The Control and Status Registers provide the user with a mechanism for changing and reading the value of various parameters of the X96011. The X96011 contains five Control, one Status, and several Reserved registers, each being one Byte wide (See Figure 4). The Control registers 0 through 6 are located at memory addresses 80h through 86h respectively. The Status register is at memory address 87h, and the Reserved registers at memory address 82h, 84h, and 88h through 8Fh. All bits in Control register 6 always power up to the logic state "0". All bits in Control registers 0 through 5 power up to the logic state value kept in their corresponding nonvolatile memory cells. The nonvolatile bits of a register retain their stored values even when the X96011 is powered down, then powered back up. The nonvolatile bits in Control 0 through Control 5 registers are all preprogrammed to the logic state "0" at the factory, except the cases that indicate "1" in Figure 1. Bits indicated as "Reserved" are ignored when read, and must be written as "0", if any Write operation is performed to their registers. A detailed description of the function of each of the Control and Status register bits follows: Control Register 0 This register is accessed by performing a Read or Write operation to address 80h of memory. ADCFILTOFF: ADC FILTERING CONTROL (NON-VOLATILE) When this bit is"1", the status register at 87h is updated after every conversion of the ADC. When this bit is "0" (default), the status register is updated after four consecutive conversions with the same result, on the 6 MSBs. NV13: CONTROL REGISTERS 1 AND 3 VOLATILITY MODE SELECTION BIT (NON-VOLATILE) When the NV13 bit is set to "0" (default), bytes written to Control registers 1 and 3 are stored in volatile cells, and their content is lost when the X96011 is powered down. When the NV13 bit is set to "1", bytes written to Control registers 1 and 3 are stored in both volatile and nonvolatile cells, and their value doesn't change when the X96011 is powered down and powered back up. See "Writing to Control Registers" on page 22. IDS: CURRENT GENERATOR DIRECTION SELECT BIT (NON-VOLATILE) The IDS bit sets the polarity of the Current Generator. When this bit is set to "0" (default), the Current Generator of the X96011 is configured as a Current Source. The Current Generator is configured as a Current Sink when the IDS bit is set to "1". See Figure 5. REV 1.8 6/24/03 www.xicor.com 11 of 25 X96011 Figure 4. Control and Status Register Format Byte Address MSB 7 80h Non-Volatile 6 5 4 3 2 1 LSB 0 Register Name 1 IDS Iout Direction 0: Source 1: Sink NV13 Control 1, 3 Volatility 0: Volatile 1: Nonvolatile ADCfiltOff ADC filtering 0: On 1: Off 0 0 0 0 Control 0 Direct Access to the LUT 81h Volatile or Non-Volatile Reserved Reserved LDA5 LDA4 LDA3 LDA2 LDA1 LDA0 Control 1 Direct Access to the DAC 83h Volatile or Non-Volatile DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Control 3 85h Non-Volatile 0 0 DDAS Direct Access to DAC 0: Disabled 1: Enabled LDAS Direct Access to LUT 0: Disabled 1: Enabled 0 0 IFSO1 IFSO0 Control 5 R Selection 00: Reserved 01: Low Internal 10: Middle Internal 11: High Internal (Default) 86h Volatile WEL Write Enable Latch 0: Write Disabled 1: Write Enabled Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control 6 ADC Output 87h Volatile AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Status Registers in byte addresses 82h, 84h, and 88h through 8Fh are reserved. Registers bits shown as 0 or 1 should always use these values for proper operation. REV 1.8 6/24/03 www.xicor.com 12 of 25 X96011 Control Register 1 This register is accessed by performing a Read or Write operation to address 81h of memory. This byte's volatility is determined by bit NV13 in Control register 0. LDA5-LDA0: LUT DIRECT ACCESS BITS When bit LDAS (bit 4 in Control register 5) is set to "1", the LUT is addressed by these six bits, and it is not addressed by the output of the on-chip A/D converter. When bit LDAS is set to "0", these six bits are ignored by the X96011. See Figure 7. A value between 00h (0010) and 3Fh (6310) may be written to these register bits, to select the corresponding row in the LUT. The written value is added to the base address of the LUT (90h). Control Register 3 This register is accessed by performing a Read or Write operation to address 83h of memory. This byte's volatility is determined by bit NV13 in Control register 0. DDA7-DDA0: D/A DIRECT ACCESS BITS When bit DDAS (bit 5 in Control register 5) is set to "1", the input to the D/A converter is the content of bits DDA7-DDA0, and it is not a row of LUT. When bit DDAS is set to "0" (default) these eight bits are ignored by the X96011. See Figure 6. Control Register 5 This register is accessed by performing a Read or Write operation to address 85h of memory. IFSO1-IFSO0: CURRENT GENERATOR FULL SCALE OUTPUT SET BITS (NON-VOLATILE) These two bits are used to set the full scale output current at the Current Generator pin, Iout, according to the following table. The direction of this current is set by bit IDS in Control register 0. See Figure 5. I1FSO1 0 0 1 1 I1FSO0 0 1 0 1 I1 Full Scale Output Current Reserved (Don't Use) 0.4mA 0.85 mA 1.3 mA (Default) LDAS: LUT DIRECT ACCESS SELECT BIT (NON-VOLATILE) When bit LDAS is set to "0" (default), the LUT is addressed by the output of the on-chip A/D converter. When bit LDAS is set to "1", LUT is addressed by bits LDA5- LDA0. DDAS: D/A DIRECT ACCESS SELECT BIT (NON-VOLATILE) When bit DDAS is set to "0" (default), the input to the D/A converter is a row of the LUT. When bit DDAS is set to "1", that input is the content of the Control register 3. Control Register 6 This register is accessed by performing a Read or Write operation to address 86h of memory. REV 1.8 6/24/03 www.xicor.com 13 of 25 X96011 WEL: WRITE ENABLE LATCH (VOLATILE) The WEL bit controls the Write Enable status of the entire X96011 device. This bit must be set to "1" before any other Write operation (volatile or nonvolatile). Otherwise, any proceeding Write operation to memory is aborted and no ACK is issued after a Data Byte. The WEL bit is a volatile latch that powers up in the "0" state (disabled). The WEL bit is enabled by writing 100000002 to Control register 6. Once enabled, the WEL bit remains set to "1" until the X96011 is powered down, and then up again, or until it is reset to "0" by writing 000000002 to Control register 6. A Write operation that modifies the value of the WEL bit will not cause a change in other bits of Control register 6. Status Register - ADC Output This register is accessed by performing a Read operation to address 87h of memory. AD7-AD0: A/D CONVERTER OUTPUT BITS (READ ONLY) This byte is the binary output of the on-chip digital thermometer. The output is 000000002 for -40C and 111111112 for 100C. The six MSBs select a row of the LUT. LOOK-UP TABLE The X96011 memory array contains a 64-byte look-up table. The look-up table is associated to pin Iout's output current generator through the D/A converter. The output of the look-up table is the byte contained in the selected row. By default this byte is the input to the D/A converter driving pin Iout. The byte address of the selected row is obtained by adding the look-up table base address 90h, and the appropriate row selection bits. See Figure 6. By default the look-up table selection bits are the 6 MSBs of the digital thermometer output. Alternatively, the A/D converter can be bypassed and the six row selection bits are the six LSBs of Control Register 1 for the LUT. The selection between these options is illustrated in Figure 6. CURRENT GENERATOR BLOCK The Current Generator pin Iout is the output of the current mode D/A converter. D/A Converter Operation The Block Diagram for the D/A converter is shown in Figure 5. The input byte of the D/A converter selects a voltage on the non-inverting input of an operational amplifier. The output of the amplifier drives the gate of a FET. This node is also fed back to the inverting input of the amplifier. The drain of the FET is connected to the output current pin (Iout) via a "polarity select" circuit block. REV 1.8 6/24/03 www.xicor.com 14 of 25 X96011 Figure 5. D/A Converter Block Diagram Vcc IDS: bit 6 in Control register 0. Internal Reference Voltage DAC Input byte Polarity Select Circuit Iout Pin Voltage Divider + - IFSO[1:0] bits 1 and 0 in Control register 5 11 10 01 Middle_Current High_Current Vss Vss Figure 6. Look-up Table (LUT) Operation DDA[7:0] : Control register 3 LUT Row Selection bits 6 A D D E R 8 LUT CFh 8 8 D1 D0 Out Select 90h DDAS: Bit 5 of Control register 5 DAC Input Byte 8 90h ... Low_Current Vss REV 1.8 6/24/03 www.xicor.com 15 of 25 X96011 By examining the block diagram in Figure 5, we see that the maximum current through pin Iout is set by fixing values for V(VRef) and R. The output current can then be varied by changing the data byte at the D/A converter input. In general, the magnitude of the current at the D/A converter output pin may be calculated by: I = (V(VRef) / (384 * R)) * N where N is the decimal representation of the input byte to the corresponding D/A converter. The value for the resistor determines the full scale output current that the D/A converter may sink or source. Bits IFSO1 and IFSO0 select the full scale output current setting for Iout as described in "IFSO1-IFSO0: Current Generator Full Scale Output Set Bits (Non-volatile)" on page 13. Bit IDS and in Control Register 0 select the direction of the currents through pins Iout (See "IDS: Current Generator Direction Select Bit (Non-volatile)" on page 11 and "Control and Status Register Format" on page 12). Figure 7. Look-Up Table Addressing D/A Converter Output Current Response When the D/A converter input data byte changes by an arbitrary number of bits, the output current changes from an intial current level (Ix) to some final level (Ix + Ix). The transition is monotonic and glitchless. D/A Converter Control The data byte inputs of the D/A converters can be controlled in three ways: - 1) With the A/D converter and through the look-up tables (default), - 2) Bypassing the A/D converter and directly accessing the look-up tables, - 3) Bypassing both the A/D converter and look-up tables, and directly setting the D/A converter input byte. Voltage Reference LDA[5:0]: 6 Control Register 1 Voltage Input from Internal temperature sensor D1 Out D0 Select ADC 8 AD[7:0] Status Register 6 LUT Row Selection bits LDAS: bit 4 in Control register 5 REV 1.8 6/24/03 www.xicor.com 16 of 25 X96011 Figure 8. D/A Converter Power on Reset Response Voltage Vcc VADCOK 0V Current Time Ix ADC TIME Ix x 10% Time The options are summarized in the following tables: D/A Converter Access Summary LDAS 0 1 X POWER ON RESET When power is applied to the Vcc pin of the X96011, the device undergoes a strict sequence of events before the current outputs of the D/A converters are enabled. When the voltage at Vcc becomes larger than the power on reset threshold voltage (VPOR), the device recalls all control bits from non-volatile memory into volatile registers. Next, the analog circuits are powered up. When the voltage at Vcc becomes larger than a second voltage threshold (VADCOK), the ADC is enabled. In the default case, after the ADC performs four consecutive conversions with the same exact result, the ADC output is used to select a byte from the look-up table. The byte becomes the input of the DAC. During all the previous sequence the input of the DAC is 00h. If bit ADCfiltOff is "1", only one ADC conversion is necessary. Bit DDAS and LDAS, also modify the way the DAC is accessed the first time after power up, as described in "Control Register 5" on page 13. The X96011 is a hot pluggable device. Voltage distrubances on the Vcc pin are handled by the power-on reset circuit, allowing proper operation during hot plugin applications. DDAS 0 0 1 Control Source A/D converter through LUT (Default) Bits LDA5-LDA0 through LUT Bits DDA7-DDA0 "X" = Don't Care Condition (May be either "1" or "0") Bit DDAS is used to bypass the A/D converter and look-up table, allowing direct access to the input of the D/A converter with the byte in control register 3. See Figure 6, and the descriptions of the control bits. Bit IDS in Control Register 0 select the direction of the current through pin Iout. See Figure 5, and the descriptions of the control bits. REV 1.8 6/24/03 www.xicor.com 17 of 25 X96011 SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. The X96011 operates as a slave in all applications. Serial Clock and Data Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 10. On power up of the X96011, the SDA pin is in the input mode. Serial Start Condition All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met. See Figure 9. Serial Stop Condition All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus. See Figure 9. Serial Acknowledge An ACK (Acknowledge), is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data. See Figure 11. The device responds with an ACK after recognition of a START condition followed by a valid Slave Address byte. A valid Slave Address byte must contain the Device Type Identifier 1010, and the Device Address bits matching the logic state of pins A2, A1, and A0. See Figure 13. If a write operation is selected, the device responds with an ACK after the receipt of each subsequent eight-bit word. In the read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state. The X96011 acknowledges all incoming data and address bytes except: 1) The "Slave Address Byte" when the "Device Identifier" or "Device Address" are wrong; 2) All "Data Bytes" when the "WEL" bit is "0", with the exception of a "Data Byte" addresses to location 86h; 3) "Data Bytes" following a "Data Byte" addressed to locations 80h, 85h, or 86h. REV 1.8 6/24/03 www.xicor.com 18 of 25 X96011 Figure 9. Valid Start and Stop Conditions SCL SDA STOP START Figure 10. Valid Data Changes on the SDA Bus SCL SDA Data Stable Data Change Data Stable Figure 11. Acknowledge Response From Receiver SCL from Master 1 8 9 SDA Output from Transmitter SDA Output from Receiver START ACK REV 1.8 6/24/03 www.xicor.com 19 of 25 X96011 X96011 Memory Map The X96011 contains a 80 byte array of mixed volatile and nonvolatile memory. This array is split up into two distinct parts, namely: (Refer to figure 12.) - Look-up Table (LUT) - Control and Status Registers Figure 12. X96011 Memory Map Address CFh 90h 8Fh 80h Size Addressing Protocol Overview All Serial Interface operations must begin with a START, followed by a Slave Address Byte. The Slave address selects the X96011, and specifies if a Read or Write operation is to be performed. It should be noted that the Write Enable Latch (WEL) bit must first be set in order to perform a Write operation to any other bit. (See "WEL: Write Enable Latch (Volatile)" on page 14.) Also, all communication to the X96011 over the 2-wire serial bus is conducted by sending the MSB of each byte of data first. The memory is physically realized as one contiguous array, organized as 5 pages of 16 bytes each. The X96011 2-wire protocol provides one address byte. The next few sections explain how to access the different areas for reading and writing. Figure 13. Slave Address (SA) Format Look-up Table (LUT) Control & Status Registers 64 Bytes 16 Bytes The Control and Status registers of the X96011 are used in the test and setup of the device in a system. These registers are realized as a combination of both volatile and nonvolatile memory. These registers reside in the memory locations 80h through 8Fh. The reserved bits within registers 80h through 86h, must be written as "0" if writing to them, and should be ignored when reading. Register bits shown as 0 or 1, in Figure 4, must be written with the indicated value if writing to them. The reserved registers, 82h, 84h, and from 88h through 8Fh, must not be written, and their content should be ignored. The LUT is realized as nonvolatile EEPROM, and extend from memory locations 90h-CFh. This LUT is dedicated to storing data solely for the purpose of setting the outputs of Current Generators IOUT. All bits in the LUT are preprogrammed to "0" at the factory. SA7 1 SA6 SA5 0 1 SA4 0 SA3 AS2 SA2 AS1 SA1 AS0 SA0 R/W Device Type Identifier Device Address Read or Write Slave Address Bit(s) SA7-SA4 SA3-SA1 SA0 Description Device Type Identifier Device Address Read or Write Operation Select REV 1.8 6/24/03 www.xicor.com 20 of 25 X96011 Slave Address Byte Following a START condition, the master must output a Slave Address Byte (Refer to figure 13.). This byte includes three parts: - The four MSBs (SA7-SA4) are the Device Type Identifier, which must always be set to 1010 in order to select the X96011. - The next three bits (SA3-SA1) are the Device Address bits (AS2-AS0). To access any part of the X96011's memory, the value of bits AS2, AS1, and AS0 must correspond to the logic levels at pins A2, A1, and A0 respectively. - The LSB (SA0) is the R/W bit. This bit defines the operation to be performed on the device being addressed. When the R/W bit is "1", then a Read operation is selected. A "0" selects a Write operation (Refer to figure 13.) Nonvolatile Write Acknowledge Polling After a nonvolatile write command sequence is correctly issued (including the final STOP condition), the X96011 initiates an internal high voltage write cycle. This cycle typically requires 5 ms. During this time, any Read or Write command is ignored by the X96011. Write Acknowledge Polling is used to determine whether a high voltage write cycle is completed. During acknowledge polling, the master first issues a START condition followed by a Slave Address Byte. The Slave Address Byte contains the X96011's Device Type Identifier and Device Address. The LSB of the Slave Address (R/W) can be set to either 1 or 0 in this case. If the device is busy within the high voltage cycle, then no ACK is returned. If the high voltage cycle is completed, an ACK is returned and the master can then proceed with a new Read or Write operation. (Refer to figure 14.). Byte Write Operation In order to perform a Byte Write operation to the memory array, the Write Enable Latch (WEL) bit of the Control 6 Register must first be set to "1". (See "WEL: Write Enable Latch (Volatile)" on page 14.) For any Byte Write operation, the X96011 requires the Slave Address Byte, an Address Byte, and a Data Byte (See Figure 15). After each of them, the X96011 responds with an ACK. The master then terminates the transfer by generating a STOP condition. At this time, if all data bits are volatile, the X96011 is ready for the next read or write operation. If some bits are nonvolatile, the X96011 begins the internal write cycle to the nonvolatile memory. During the internal nonvolatile write cycle, the X96011 does not respond to any requests from the master. The SDA output is at high impedance. Writing to Control bytes which are located at byte addresses 80h through 8Fh is a special case described in the section "Writing to Control Registers" . Page Write Operation The 80-byte memory array is physically realized as one contiguous array, organized as 5 pages of 16 bytes each. A "Page Write" operation can be performed to any of the four LUT pages. In order to perform a Page Write operation, the Write Enable Latch (WEL) bit in Control register 6 must first be set (See "WEL: Write Enable Latch (Volatile)" on page 14.) Figure 14. Acknowledge Polling Sequence Byte load completed by issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) Issue STOP ACK returned? NO YES High Voltage complete. Continue command sequence. NO YES Continue normal Read or Write command sequence Issue STOP PROCEED REV 1.8 6/24/03 www.xicor.com 21 of 25 X96011 Figure 15. Byte Write Sequence Write Signals from the Master S t a r t Slave Address Address Byte Data Byte S t o p Signal at SDA Signals from the Slave 10 10 0 A C K A C K A C K A Page Write operation is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to 16 bytes (See Figure 16). After the receipt of each byte, the X96011 responds with an ACK, and the internal byte address counter is incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and goes back to the first byte of the same page. For example, if the master writes 12 bytes to a 16-byte page starting at location 11 (decimal), the first 5 bytes are written to locations 11 through 15, while the last 7 bytes are written to locations 0 through 6 within that page. Afterwards, the address counter would point to location 7. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time (See Figure 17). The master terminates the loading of Data Bytes by issuing a STOP condition, which initiates the nonvolatile write cycle. As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. A Page Write operation cannot be performed on the page at locations 80h through 8Fh. Next section describes the special cases within that page. Writing to Control Registers The bytes at locations 80h, 81h, 83h, 85h, and 86h are written using Byte Write operations. They cannot be written using a Page Write operation. Registers Control 1 and 3 have a nonvolatile and a volatile cell for each bit. At power up, the content of the nonvolatile cells is automatically recalled and written to the volatile cells. The content of the volatile cells controls the X96011's functionality. If bit NV13 in the Control 0 register is set to "1", a Write operation to these registers writes to both the volatile and nonvolatile cells. If bit NV13 in the Control 0 register is set to "0", a Write operation to these registers only writes to the volatile cells. In both cases the newly written values effectively control the X96011, but in the second case, those values are lost when the part is powered down. If bit NV13 is set to "0", a Byte Write operation to Control registers 0 or 5 causes the value in the nonvolatile cells of Control registers 1 and 3 to be recalled into their corresponding volatile cells, as during power up. Figure 16. Page Write Operation Write Signals from the Master S t a r t 2 < n < 16 Slave Address Address Byte S t o p Data Byte (1) Data Byte (n) Signal at SDA 10 10 Signals from the Slave 0 A C K A C K A C K A C K REV 1.8 6/24/03 www.xicor.com 22 of 25 X96011 Figure 17. Example: Writing 12 bytes to a 16-byte page starting at location 11. 7 bytes 5 bytes 5 bytes Address=0 Address=6 Address=7 Address Pointer Ends Up Here Address=11 Address=15 This doesn't happen when the WP pin is LOW, because Write Protection is enabled. It is generally recommended to configure Control registers 0 and 5 before writing to Control registers 1 or 3. A "Byte Write" operation to Control register 1 or 3, causes the value in the nonvolatile cells of the other to be recalled into the corresponding volatile cells, as during power up. When reading either of the control registers 1 or 3, the Data Bytes are always the content of the corresponding nonvolatile cells, even if bit NV13 is "0" (See "Control and Status Register Format"). Read Operation A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 18). The master initiates the operation issuing the following sequence: a START, the Slave Address byte with the R/W bit set to "0", an Address Byte, a second START, and a second Slave Address byte with the R/W bit set to "1". After each of the three bytes, the X96011 responds with an ACK. Then the X96011 transmits Data Bytes as long as the master responds with an Figure 18. Read Sequence Signals from the Master S t a r t Slave Address with R/W=0 S t a r t ACK during the SCL cycle following the eigth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (See Figure 18). The Data Bytes are from the memory location indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location CFh a stop should be issued. If the read operation continues the output bytes are unpredictable. If the byte address is set between 00h and 7Fh, or higher than CFh, the output bytes are unpredictable. A Read operation internal pointer can start at any memory location from 80h through CFh, when the Address Byte is 80h through CFh respectively. When reading any of the control registers 1, 2, 3, or 4, the Data Bytes are always the content of the corresponding nonvolatile cells, even if bit NV13 is "0" (See "Control and Status Register Format"). Address Byte Slave Address with R/W=1 A C K A C K S t o p Signal at SDA Signals from the Slave 10 10 0 A C K A C K 10 10 1 A C K First Read Data Byte Last Read Data Byte REV 1.8 6/24/03 www.xicor.com 23 of 25 X96011 Data Protection There are three levels of data protection designed into the X96011: 1- Any Write to the device first requires setting of the WEL bit in Control 6 register; 2- The Write Protection pin disables any writing to the X96011; 3- The proper clock count, data bit sequence, and STOP condition is required in order to start a nonvolatile write cycle, otherwise the X96011 ignores the Write operation. WP: Write Protection Pin When the Write Protection (WP) pin is active (LOW), any Write operations to the X96011 is disabled, except the writing of the WEL bit. REV 1.8 6/24/03 www.xicor.com 24 of 25 X96011 PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Code V14 .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .041 (1.05) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail "A" NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) Seating Plane LIMITED WARRANTY (c)Xicor, Inc. 2003 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, BiasLock and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.8 6/24/03 www.xicor.com Characteristics subject to change without notice. 25 of 25 |
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